1. Field of the Invention
This invention relates generally to methods and structures for improving the fabrication of multilevel interconnects in integrated circuits and more particularly to a system and method for optimizing a trench etch for a damascene application without an intermediate etch stop layer.
2. Description of the Related Art
As microprocessor speeds push toward 1 GHz and eventually beyond, radical changes in fabrication technology will be needed. Among these is the adoption of copper as an interconnect material. However, copper interconnect fabrication presents formidable challenges, as it is difficult to etch copper. Because of the increased use of Cu as an interconnect conductor and its challenges with the current fabrication methods, a contemporaneous interest in damascene fabrication methods has been pursued since damascene methods have shown the greatest promise for production worthy copper interconnect fabrication.
Damascene processes typically include, a trench or canal cut into the dielectric, the trench or canal then being filled with metal. In dual damascene processing, a second hole or via is formed within the trench. Implementation of the damascene methods proceeds by either the self-aligned dual damascene (SADD), trench first or via first approach. Of these three approaches, the SADD method is most difficult to control because of challenging lithography alignment requirements. Both trench first and via first have much greater and nearly equal tolerance for lithographic alignment error.
These damascene approaches may be implemented with an intermediate etch stop layer. The material commonly used for intermediate etch stop layers (e.g., silicon nitride) has a relatively high dielectric constant and can increase the capacitance of the dielectric stack. For example, an 800 xc3x85 silicon nitride stop layer can increase layer to layer interconnect coupling capacitance by about as much as 7% to 10%. As such, the use of intermediate etch stop layers increases fabrication cost and time because processes to apply and then remove the intermediate etch stop layer must be performed. Therefore, the removal of the intermediate etch stop layer is advantageous for device performance and cost. However, without the intermediate etch stop layers, stringent trench etch requirements for etch uniformity must be imposed on the damascene approaches.
The final trench profile of the damascene approaches described above is expected to have a rectangular cross section, which must be uniform across the wafer. One of the functions of the intermediate etch stop layer is to create a flat and uniform trench bottom profile. Departures from this standard profile make it difficult to control line resistance and to estimate trench critical dimension (CD) from line resistance data. Furthermore, device simulation codes typically assume rectangular cross sections to reduce computation time and cost. When the actual profiles depart this shape, comparison with simulated results becomes very difficult or even impossible.
In the absence of a stop layer, obtained trench bottom profiles are either microtrenched (xe2x80x9cWxe2x80x9d shaped) or bottom rounded (xe2x80x9cUxe2x80x9d shaped) profiles. It is inherently more difficult to get good seed layer coverage on microtrenched profiles. The very high curvature at the microtrench bottoms also results in high electric fields at these high curvature points and invites reduction of the dielectric breakdown voltage threshold. Solely trying to modulate the microtrenching in order to achieve a flat trench bottom profile without consideration of the ion and neutral limited regimes has not been successful. Vyvoda et al. discuss this approach in a paper entitled xe2x80x9cEffects of plasma conditions on the shapes of features etched in Cl2 and HBr plasmas. I. Bulk crystalline silicon etchingxe2x80x9d, dated November/December 1998,which is herein incorporated by reference. Alternatively, bottom rounding is typically aspect ratio dependent which may lead to a loss of line resistance control.
As a result, there is a need to solve the problems of the prior art to provide a substantially flat and uniform trench profile across the wafer in the absence of an intermediate etch stop layer.
Broadly speaking, the present invention fills these needs by providing a method for etching substantially flat and uniform trench profile across a wafer in the absence of an intermediate etch stop layer. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, or a device. Several inventive embodiments of the present invention are described below.
In one embodiment, a method for etching a trench profile into a dielectric layer is provided. In this embodiment, an ion-to-neutral flux ratio is controlled during etching so as to achieve a neutral limited regime in an ion assisted etch mechanism, thereby causing bottom rounding. Additionally, physical sputtering is modulated so as to cause microtrenching to offset the bottom rounding so as to produce a substantially flat bottom trench profile.
In another embodiment, a method for etching trenches in a dielectric layer of a wafer in an etch chamber is provided. The etch chamber includes a top and bottom electrode, a chuck for holding the wafer and process gas inlets. The method for etching trenches in the dielectric layer includes applying process gases into the chamber and applying radio frequency (RF) power to the top and bottom electrodes. The method for etching further includes controlling an ion to neutral flux ratio so as to achieve a neutral limited regime in an ion assisted etch mechanism where the neutral regime causes bottom rounding and modulating physical sputtering, which causes microtrenching to offset the bottom rounding so as to produce a substantially flat trench bottom profile.
The advantages of the present invention are numerous. Most notably, the elimination of the intermediate stop layer will decrease fabrication cost and process time. Additionally, the elimination of the intermediate stop layer in dual damascene processes will improve device performance since a typical silicon nitride stop layer can increase layer to layer interconnect coupling capacitance by about as much as 7% to 10%.